Onboard Computing & Avionics
Onboard computers and avionics for CubeSats and SmallSats.
Custom development
We design onboard computers, payload processors, ADCS computers and interface electronics. Processing architecture, memory, connectivity and fault recovery are configured around the spacecraft and its payload.
- CubeSat & SmallSat
- MCU and processor/FPGA
- Hardware + firmware
Key features
Processing and data handling
- Low-power microcontroller architectures for spacecraft control and subsystem management.
- Application-processor and processor/FPGA architectures for payload data handling.
- Dedicated hardware acceleration for filtering, data formatting, compression and interface processing.
- Separation of essential spacecraft control from computationally intensive payload tasks.
- Power modes and workload scheduling matched to available spacecraft energy.
Memory and persistence
- Volatile working memory sized for execution load, buffering and timing requirements.
- Nonvolatile boot and recovery storage using internal flash or external NOR flash.
- FRAM or other mission-selected nonvolatile memory for parameters, counters and event records.
- NAND or eMMC storage options for payload files and recorded telemetry.
- Error detection and correction, scrubbing and memory-health reporting matched to the selected devices.
- Redundant configuration copies, integrity checks and recovery from interrupted writes.
Timing, supervision and recovery
- Real-time clock, external timing input and pulse-per-second synchronization.
- Hardware timestamps and trigger interfaces for payload and sensor coordination.
- External hardware watchdogs independent of normal application execution.
- Supply supervision, brownout detection and controlled reset sequencing.
- Protected bootloader, recovery image, trial boot and rollback.
- Fault counters, reset-cause reporting and persistent diagnostic records.
- Selective device reset and coordination with EPS power cycling.
Interface and configuration options
| Area | Design options |
|---|---|
| Spacecraft networks | CAN, CAN FD, RS-422, RS-485 and UART-based equipment links |
| Payload data | SpaceWire, Ethernet and FPGA-defined LVDS interfaces |
| Board-level devices | SPI, I²C, GPIO, ADC inputs and PWM outputs |
| Timing | PPS input/output, event capture, real-time clock and payload triggers |
| Development | SWD or JTAG, USB or serial debug console and engineering-model access |
| Software platform | Bare metal or RTOS control; embedded Linux on selected payload-processing architectures |
| Packet services | CSP, CCSDS Space Packets and mission-specific command/telemetry services |
| Protection | Watchdogs, supervised supplies, memory protection and controlled recovery |
| Redundancy | Single-string, dual-computer or selected redundant-interface architectures |
| Packaging | Compact stackable boards, PC/104-style mechanical layouts, custom footprints or enclosed SmallSat units |
Options are selected per design; they are not all simultaneous features of a single board. Stack connectors and pin assignments are defined in the interface control document.
Configuration examples
| Configuration | Typical engineering scope |
|---|---|
| CubeSat control computer | MCU-based control, protected boot, persistent configuration, CAN/serial equipment links and compact packaging |
| Integrated avionics module | OBC combined with selected sensor interfaces, ADCS processing or radio-control functions |
| SmallSat onboard computer | Distributed interfaces, tailored fault containment, selected redundancy and enclosed packaging |
| Payload data processor | Processor/FPGA computing, larger storage, high-throughput links and payload-specific processing |
Firmware and development tools
Board support packages, bootloaders and drivers are developed with the electronics. Command dictionaries, telemetry definitions, example applications, interface libraries and configuration tools support integration with customer flight software and ground equipment.
Verification and delivery
Interface loading, timing, processor utilization, storage integrity and recovery behavior are verified on the target hardware. Tests exercise interrupted updates, power loss, communication faults and watchdog decisions. Delivery combines assembled hardware, firmware, interface documentation, configuration records and test results.